// Copyright (C) 1953-2022 NUDT
// Verilog module name - delay_process 
// Version: V4.3.0.20230902
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module delay_process(
input                 i_clk,
input                 i_rst_n,

input                 i_teststart_en,
input      [63:0]     iv_delaydata,
input                 i_delaydata_wr,
output reg [63:0]     ov_delay_jitter,  
output reg [63:0]     ov_max_delay,  
output reg [63:0]     ov_min_delay
);         

always@(posedge i_clk or negedge i_rst_n)begin 
    if(!i_rst_n) begin
		ov_max_delay	<=64'd0;
		ov_delay_jitter <=64'd0;
		ov_min_delay    <=64'hffffffffffffffff;
    end
    else begin	
		if(i_delaydata_wr==1'b1)begin//trans delay
			ov_delay_jitter<=ov_max_delay-ov_min_delay;
			if(iv_delaydata>ov_max_delay)begin
				ov_max_delay <=iv_delaydata;
			end			
			else begin 
				ov_max_delay <=ov_max_delay;
			end
			if(iv_delaydata<ov_min_delay)begin
				ov_min_delay <=iv_delaydata;
			end			
			else begin 
				ov_min_delay <=ov_min_delay;
			end
		end	
		else begin
			ov_delay_jitter <=ov_delay_jitter;
			ov_max_delay	<= ov_max_delay;
			ov_min_delay    <= ov_min_delay;		
		end
    end       
end	
endmodule
/*
delay_process delay_process_inst(
.i_clk          (    ),               
.i_rst_n        (    ),    
   
.i_teststart_en (    ),
.iv_delaydata   (    ),
.i_delaydata_wr (    ),
.ov_delay_jitter(    ),
.ov_max_delay   (    ),
.ov_min_delay   (    )
)
*/